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A serial/parallel converter is an interface circuit in high-speed data communication. Serial/parallel converters are very common in the field of high-speed data communication. They play an important role not only in optical fiber data transmission, but also in short-distance chip interconnection, similar to the importance of twisted pair cables in networking. They can effectively reduce the number of pins and traces, and improve the data transmission rate.
Principle:
Serializers and deserializers achieve data transmission by converting parallel data into serial data (serializers) or converting serial data into parallel data (deserializers).
Main structure:
Source synchronous interface: This structure can use a reference clock source as the clock for capturing data, or it can receive data using the clock sent by the data transmitter, so a clock data recovery circuit is not necessary. This structure can solve two main problems caused by parallel connections. Firstly, by serializing the parallel data to k data bits (reducing the number of channels to k), the physical consumption is reduced. At the receiving end, the k data bits are deserialized back to n data bits.
Pre-clock: A high-speed clock signal path is added between the two chips. The clock source only needs to provide a lower frequency clock signal, which is multiplied by the phase-locked loop inside the two chips to the required clock frequency for sending and receiving data. The clock signal output by chip 1, generated by the phase-locked loop, is used to send data and is also connected as an input to chip 2 to capture data. This improved structure is called a pre-clock structure.
Data grouping by difference: Since the device receiving the differential signal determines whether a data bit is 1 or 0 based on the difference between the two signals, rather than the individual signal's voltage level, differential-driven circuits tend to have linear current consumption and produce less noise than single-ended signals. The structure using differential output, as shown in the diagram, effectively increases the eye diagram's opening angle for a given clock connection path by only pairing with a certain number of data channels. To expand the opening angle of the eye diagram, the clock tree and the path from each data flip-flop to the clock output should be shared by as many circuits as possible, and the driving of the clock should be equivalent to the driving of the data. Ideally, a clock driver should drive the clock signal to the output driver while also driving the clock input to each data flip-flop, but this becomes more difficult as the number of data bus bits increases. The farther apart two circuits are, the greater the impact of PVT, and the more circuits cannot be shared by the clock distribution network.
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